1. Field of the Invention
Embodiments of the present invention relate generally to image sensor circuits and methods and, in specific embodiments, to image sensor circuits with column readout lines for columns of pixel circuits.
2. Related Art
Image sensors have found wide application in consumer and industrial electronics, and have enabled an explosion in a number of digital cameras and digital video devices used for work and entertainment. In many applications, and especially in industrial applications, there is a constant demand for image sensors with faster processing speed and better image quality. Thus, it is advantageous to develop new architectures that allow for improved performance of image sensor circuits.
FIG. 1 illustrates an architecture of a related art image sensor circuit 210. As illustrated in FIG. 1, the image sensor circuit 210 comprises a pixel array 220, a row decoder/driver 224, an analog-to-digital conversion (ADC) block 230, an ADC controller 234, a memory 241, a memory controller 244, a readout bus 245, sense amplifiers 246, pad drivers 248, and pads 250. The pixel array 220 comprises pixel circuits 2 that are arranged in rows and columns. Each pixel circuit 2 comprises a light sensitive element, such as a photodiode, or the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel circuit 2 is configured to produce an analog pixel signal based on the sampled light intensity.
The row decoder/driver 224 supplies control signals to the pixel circuits 2 in the pixel array 220 to control an operation of the pixel circuits 2. Pixel circuits 2 that are in a same row of the pixel array 220 may share a common row control signal from the row decoder/driver 224. Pixel circuits 2 that are in a same column of the pixel array 220 share a common column readout line to provide output. For example, pixel circuits 2 in a first column of the pixel array 220 share a column readout line 2221, pixel circuits 2 in a second column of the pixel array 220 share a column readout line 2222, and pixel circuits 2 in an Mth column of the pixel array 220 share a column readout line 222M. The row decoder/driver 224 typically controls the pixel circuits 2 to perform processing row by row.
The analog pixel signals output from the pixel array 220 are input to the ADC block 230. The ADC block 230 typically comprises one ADC circuit 3 for each column of pixel circuits 2 in the pixel array 220. Each ADC circuit 3 is configured to convert analog pixel signals received from the pixel array 220 into corresponding digital pixel signals. The ADC controller 234 controls an operation of the ADC circuits 3, and may also control an operation of the row decoder/driver 224. The ADC block 230 outputs digital pixel signals from the ADC circuits 3.
The digital pixel signals output from the ADC block 230 are input to the memory 241. The memory 241 may comprise, for example, random access memory (RAM) cells RAM0 242 and RAM cells RAM1 243. Each RAM cell RAM0 242 stores bits from a digital pixel signal output from a-corresponding ADC circuit 3. The bits stored in each RAM cell RAM0 242 are then output and stored into a corresponding RAM cell RAM1 243. The bits stored in each RAM cell RAM1 243 are then output on readout bus 245 to sense amplifiers 246. The readout bus 245 typically comprises multiple bit lines, so that multiple bits may be transferred simultaneously. The memory controller 244 controls an operation of the RAM cells RAM0 242 and the RAM cells RAM1 243. The outputs of the sense amplifiers 246 are provided to pad drivers 248, and the pad drivers 248 drive digital signals to pads 250 that are located in various positions on the image sensor circuit 210.
Further examples of related art image sensor circuits are disclosed in the following references: (i) U.S. Pat. No. 6,870,565 entitled “Semiconductor Imaging Sensor Array Devices with Dual-Port Digital Readout”, the contents of which are incorporated by reference herein; (ii) U.S. Patent Application Publication Number 2003/0043089 entitled “Doubling of Speed in CMOS Sensor with Column-Parallel ADCs”, the contents of which are incorporated by reference herein; and (iii) A. Krymski et al., “A High Speed, 500 Frames/s, 1024×1024 CMOS Active Pixel Sensor”, 1999 Symposium on VLSI Circuits Digest of Technical Papers, 1999, Kyoto, Japan, pp. 137-138, the contents of which are incorporated by reference herein.